Damascene processing is a method for forming metal lines on integrated circuits. It is often a preferred method because it requires fewer processing steps than other methods and offers a higher yield. In Damascene processing, as well as other integrated circuit manufacturing processes, the conductive routes on the surface of the circuit are generally formed out of a common metal, traditionally aluminum. Copper is a favored metal because of its higher conductivity and electromigration resistance when compared to aluminum, but copper presents special challenges because it readily diffuses into silicon oxide and reduces its electrical resistance at very low doping levels.
During integrated circuit fabrication, conductive metal is needed on the active circuit region of the wafer, i.e., the main interior region on the front side, but is undesirable elsewhere. In a typical copper Damascene process, the formation of the desired conductive routes generally begins with a thin physical vapor deposition (PVD) of the metal, followed by a thicker electrofill layer (which is formed by electroplating). The PVD process is typically sputtering. In order to maximize the size of the wafer's useable area (sometimes referred to herein as the “active surface region”) and thereby maximize the number of integrated circuits produced per wafer), the electrofilled metal must be deposited to very near the edge of the semiconductor wafer. Thus, it is necessary to allow physical vapor deposition of the metal over the entire front side of the wafer. As a byproduct of this process step, PVD metal typically coats the front edge area outside the active circuit region, as well as the side edge, and to some degree, the backside. Electrofill of the metal is much easier to control, since the electroplating apparatus can be designed to exclude the electroplating solution from undesired areas such as the edge and backside of the wafer. One example of plating apparatus that constrains electroplating solution to the wafer active surface is the SABRE™ clamshell electroplating apparatus available from Novellus Systems, Inc. of San Jose, Calif. and described, for example, in U.S. Pat. No. 6,800,187, “CLAMSHELL APPARATUS FOR ELECTROCHEMICALLY TREATING SEMICONDUCTOR WAFERS” naming Jonathan Reid et al. as inventors, and filed Aug. 10, 2001, which is herein incorporated by reference in its entirety for all purposes.
The PVD metal remaining on the wafer edge after electrofill is undesirable for various reasons. One reason is that PVD metal layers are thin and tend to flake off during subsequent handling, thus generating undesirable particles. This can be understood as follows. At the front side edge of the wafer, the wafer surface is beveled. Here the PVD layers are not only thin, but also unevenly deposited. Thus, they do not adhere well. Adhesion of subsequent dielectric layers onto such thin metal is also poor, thus introducing the possibility of even more particle generation. By contrast the PVD metal on the active interior region of the wafer is simply covered with thick, even electrofill metal which is eventually planarized by CMP down to the dielectric. This flat surface, which is mostly dielectric, is then covered with a barrier layer substance such as SiN that both adheres well to the dielectric and aids in the adhesion of subsequent layers. Another reason to remove the residual PVD metal layers in the wafer edge area is that the barrier layers underneath them are also thin and uneven, which may allow migration of the metal into the dielectric. This problem is especially important when the metal is copper.
To address these problems, semiconductor equipment may have to allow etching of the unwanted residual metal layers. Depending upon the type of metal to be removed and the characteristics of the etching system, some liquid etchant compositions are appropriate and others are not. In general, the liquid etchant should etch the unwanted metal rapidly at room temperature. But, it should not aggressively attack the mechanical and electrical components of the etch system. In addition, it should not liberate dangerous, gaseous by-products during the etching reaction. For example, nitric acid should be avoided because it liberates nitric oxide during reaction with copper. Still further, the components of the liquid etchant should include only those materials readily available in normal integrated circuit manufacturing facilities (FAB's), for example, a deionized water flow and reagents such as sulfuric acid and hydrogen peroxide.
Apparatus for processing wafers, for example, removing unwanted metal, are typically called a “post-electrofill module” (PEM). Examples of PEM's include “EBR modules” which are specifically designed to carry out the edge bevel removal (EBR) process, as well as a backside etch (BSE) process. Post electrofill processes often require an available flow of high purity deionized water. This high purity water is used as a solvent both to prepare etchant solutions as well as to rinse wafers, sometimes both before and after an etch step. One problem associated with post-electrofill processes is limited throughput associated with, for example, the time required to etch, acid wash, rinse and dry wafers in post-electrofill processing. Etchants take time to remove the desired amount of metal, deionized rinse steps require sufficient time to remove used etchant or acid wash, and it takes time to dry the wafer properly when needed as part of a post-electrofill process.
Another issue associated with post-electrofill processing is the amount of solvents or reagents used to effectively carry out each process step. Using highly purified solvents and reagents is expensive, so any steps taken to minimize this usage reduce the overall cost of the circuits made from each silicon wafer.
In view of these considerations, what is needed are methods and apparatus that decrease time required, and the amount of solvents and reagents used for post-electrofill processes that use deionized water. The present invention addresses these concerns.